Semiconductor test apparatus

ABSTRACT

Good device PASS/FAIL determination is realized by measuring timings of both signals, i.e., a cross point of differential clock signals CLK and a data signal DATA output from a DUT, and obtaining a relative phase difference between both signals. A semiconductor test apparatus comprises differential signal timing measurement means for outputting cross point information Tcross obtained by measuring a timing of a cross point of one of differential signals output from the device under test, non-differential signal timing measurement means for outputting data change point information Tdata obtained by measuring a timing of transition of a logic of the other non-differential signal output from the DUT, phase difference calculation means for outputting a phase difference ΔT obtained by calculating a relative phase difference between the cross point information Tcross and the data change point information Tdata obtained by simultaneously measuring both of the output signals, and PASS/FAIL determination means for determining PASS/FAIL of a relative positional relation of the DUT based on a predetermined threshold value for executing PASS/FAIL determination upon reception of the phase difference ΔT.

TECHNICAL FIELD

The present invention relates to a semiconductor test apparatus fortesting a device under test (DUT) which outputs a differential clocksignal. More particularly, the invention relates to a semiconductor testapparatus for testing a relative phase difference between a cross pointof one differential clock signal CLK output from the DUT and the otherdata signal DATA output from the DUT.

BACKGROUND ART

Background arts concerning the application will be described. JapanesePatent Application No. 2000-178917 (semiconductor device testingmethod/semiconductor device testing apparatus) discloses a testingmethod of highly accurately testing a semiconductor device which outputsa reference clock DQS used for data transfer in synchronization withdata reading within a short time.

Japanese Patent Application No. 2000-9113 (semiconductor device testingmethod/semiconductor device testing apparatus) discloses a testingmethod of highly accurately testing a semiconductor device which outputsa reference clock DQS used for data transfer in synchronization withdata reading within a short time.

Additionally, Japanese Patent Application No. 2000-204757 (semiconductordevice testing method/semiconductor device testing apparatus) disclosesa testing method of determining a failure based on a phase differencebetween a reference clock and data in a semiconductor device whichoutputs the reference clock in synchronization with data reading andoutputting and uses the reference clock for data transfer.

However, since a cross point of the differential clock signals CLKcannot be specified by the background arts, it is impossible toaccurately determine PASS/FAIL based on a relative phase differencebetween the differential clock signal and the other signal.

Next, problems concerning the present invention will be described.

FIG. 6(a) shows a principle circuit connection when high-speed datatransfer is executed between two devices on a circuit board or the likein synchronization with a differential clock output as a balancedsignal, which is used for differential transmission such as ECL or LVDS.

Differential clock signals CLK (positive clock signal CLKP, negativeclock signal CLKN) are output from a differential driver DR1 of a device1, and supplied through a transmission line to a differential receiverRCV2 of a device 2. One or a plurality of data signals DATA synchronizedwith a clock are supplied from a flip-flop FF1 of the device 1 to aninput terminal of a flip-flop FF2 of the device 2, and retimed by aclock of the differential receiver RCV2 to be used. Incidentally, in thedifferential clock signal, a variance of output amplitude occurs due toan IC manufacturing variance, phase shifting occurs between differentialsignals due to circuitry, or other problems occur. Further, some jittercomponents may be contained in the differential clock or the data TADA,or common mode noise may be generated.

Thus, in consideration of the foregoing, the device 1 that becomes adevice under test (DUT) is required to output signals based on aprescribed phase relation between a clock and data. A semiconductor testapparatus must be able to determine PASS/FAIL by measuring outputting ofthe differential clock signal and the data DATA based on the prescribedphase relation. Incidentally, the differential driver DR1 can becontrolled to a high impedance state by turning off the output. Thus,there is a need to be able to test this driver.

FIG. 6(b) shows a main portion of the semiconductor test apparatus whichcomprises a comparator CP used in a single end (unbalanced type) form toreceive each of the positive clock signal CLKP and the negative clocksignal CLKN that are differential clock signals output from the DUT.Here, the semiconductor test apparatus is constituted such thatcomparators CP of 2-channel single ends individually receive thedifferential clock signals output from the DUT because of a need tomeasure each. For example, a reason is that there is a test item in thehigh impedance state (Hi-Z mode) of the differential clock signal of theDUT, and there is a need to be able to test this item.

In FIGS. 6 a and 6 b, the first comparator CP receives one positiveclock signal CLKP, and converts the signal into a logical signal at apredetermined threshold level Vref. A timing comparator TC receives thelogical signal, and determines PASS/FAIL based on a signal held by astrobe signal STRB of a desired timing.

The second comparator CP receives the other negative clock signal CLKN,and converts the signal into a logical signal at a predeterminedthreshold level Vref. The timing comparator receives the logical signal,and determines PASS/FAIL for the individually input single end signalbased on a signal held by a strobe signal STRB of a desired timing.

Now, in the case of an ideal differential signal of FIG. 7 a, a crosspoint (point A in FIG. 7 a) of clock signals only needs be convertedinto a logical signal at a threshold level Vref of an intermediatevoltage which is ½ of amplitude.

However, as shown in an actual differential signal example of FIG. 7 b,if a cross point is converted into a logical signal at a threshold levelVref, it is detected as a cross point (point C in FIG. 7 b) shifted froma target cross point (point B in FIG. 7 b). Consequently, a problem of atiming shift (difference E in FIG. 7 b) occurs between the two crosspoints, causing accuracy deterioration of timing measurement.Especially, when a clock frequency becomes several hundred MHz orhigher, an influence of measuring accuracy is increased. As thesemiconductor test apparatus is a measuring device in which highlyaccurate timing measurement is necessary, this poses a serious practicalproblem.

FIG. 7 c shows a case in which in simultaneous measurement of bothsignals, i.e., a differential clock signal CLK and a data signal DATA,jitters such as inter-signal interference noise or power supply noisecause an inphase change between the two signals. In this case, aninstantaneous relative phase difference Δf between the two signals issmall. PASS/FAIL determination must be made to judge whether it iswithin a normal phase range or not by measuring such an instantaneousphase difference Δf1.

Conversely, FIG. 7 d shows a case in which in simultaneous measurementof both signals, i.e., a differential clock signal CLK and a data signalDATA, jitters cause a reversed phase change between the two signals. Inthis case, an instantaneous relative phase difference Δf between the twosignals is increased. PASS/FAIL determination must be made to judgewhether it is within a normal phase rage or not by measuring aninstantaneous phase difference Δf2 caused by the jitters. Apparently, itis necessary to determine PASS/FAIL by simultaneously measuring therelative phase difference between the two signals.

As described above, the single end comparators CP are applied to the twochannels to specify the position of the cross point of the differentialclock signals CLK. However, the accurate specifying is impossiblebecause the phase difference, the amplitude difference or the likebetween the positive clock signal CLKP and the negative clock signalCLKN causes the movement of the cross point.

To accurately evaluate phases of both signals, i.e., the differentialclock signal CLK and the data signal DATA, both signals must besimultaneously sampled and measured, the cross point of the differentialclock signals CLK must be specified, and the phases of the specifiedcross point and the data signal DATA must be evaluated.

However, according to the conventional technology, it is impossible todetermine PASS/FAIL by accurately obtaining a relative phase differencebetween the two signals, i.e., the cross point of the differential clockCLK and the data signal DATA. As the semiconductor test apparatus is themeasuring device in which highly accurate timing measurement isnecessary, this poses an unfavorable practical problem.

Therefore, an object of the invention is to provide a semiconductor testapparatus which can realize good device PASS/FAIL determination by using2-channel single end comparators CP, measuring and specifying a timingof a cross point of differential clock signals output from a DUT,measuring a timing of the other data signal DATA output from the DUT,and obtaining a relative phase difference between the two signals.

Another object is to provide a semiconductor test apparatus which canaccurately measure and obtain a cross point of differential clocksignals output from a DUT by using 2-channel single end comparators CP.Another object is to provide a semiconductor test apparatus which canspecify a relative phase difference between a differential signal outputfrom a DUT and the other single end signal or differential signal outputfrom the DUT. Another object is to provide a semiconductor testapparatus which can measure relative jitter amounts of a differentialsignal output from the DUT and the other signal output from the DUT.

DISCLOSURE OF THE INVENTION

First solving means of the present invention will be described. FIGS. 4and 1 show solving means concerning the invention.

To solve the problems, a semiconductor test apparatus is characterizedby comprising:

-   -   differential signal timing measurement means (e.g., cross point        measurement section 600) for outputting cross point information        Tcross obtained by measuring a timing of a cross point of        differential signals output from a device under test (DUT);    -   non-differential signal timing measurement means (e.g., data        measurement means 300) for outputting data change point        information Tdata obtained by measuring a timing of transition        of a logic of the other non-differential (single end) signal        output from the DUT;    -   phase difference calculation means (e.g., phase difference        calculation section 400) for outputting a phase difference ΔT        obtained by calculating a relative phase difference between the        cross point information Tcross and the data change point        information Tdata obtained by simultaneously measuring both of        the output signals; and    -   PASS/FAIL determination means (e.g., PASS/FAIL determination        section 500) for determining PASS/FAIL of a relative positional        relation of the DUT based on predetermined upper and lower limit        threshold values for executing PASS/FAIL determination upon        reception of the phase difference ΔT or one of the threshold        values.

According to the invention, a comparator CP of a 2-channel signal end isused, the timing of the cross point of differential signals output fromthe DUT is measured to be specified, the timing of the other data signalDATA output from the DUT is measured, and the relative phase differencebetween both signals is obtained. Thus, it is possible to realize thesemiconductor test apparatus which can execute good device PASS/FAILdetermination.

Next, second solving means will be described. FIG. 13 shows solvingmeans concerning the invention.

A semiconductor test apparatus is characterized by comprising:

-   -   first differential signal timing measurement means (e.g., cross        point measurement section 600) for outputting first cross point        information Tcross obtained by measuring a timing of a cross        point of first differential signals output from a device under        test (DUT);    -   second differential signal timing measurement means (e.g., cross        point measurement section 600) for outputting second cross point        information Tcross obtained by measuring a timing of a cross        point of the other second differential signals output from the        DUT;    -   phase difference calculation means (e.g., phase difference        calculation section 400) for outputting a phase difference ΔT        obtained by calculating a relative phase difference between the        first cross point information Tcross and the second cross point        information Tcross which are obtained by simultaneously        measuring both of the output differential signals; and    -   PASS/FAIL determination means (e.g., PASS/FAIL determination        section 500) for determining PASS/FAIL of the DUT upon reception        of the phase difference ΔT based on predetermined upper and        lower limit threshold values corresponding to the DUT whose        PASS/FAIL is determined or one of the threshold values.

Thus, it is possible to determine PASS/FAIL of the relative phasedifference by specifying the relative phase difference between the twotypes of differential signals.

Next, third solving means will be described. FIG. 4, FIGS. 5 a to 5 c,and FIG. 1 show solving means concerning the invention.

To solve the problems, a semiconductor test apparatus which highlyaccurately measures a relative phase difference between a cross pointand the other data signal DAT output from a device under test (DUT) byusing a timing of the cross point of differential signals output fromthe DUT as a reference is characterized by comprising:

-   -   first transition information measurement means (e.g., first        transition information collection means 100#1) for converting        the signals into logical signals at predetermined threshold        levels VOH, VOL for measuring two points before and after the        cross point with respect to a transition waveform of one of the        output differential signals, sampling and measuring the signals        based on a multiphase strobe signal of a known timing,        converting the signals into code data, and then outputting the        code data as two bits of timing information;    -   second transition information measurement means (e.g., second        transition time information collection means 100#2) for        converting the signals into logical values at predetermined        threshold levels VOH, VOL for measuring two points before and        after the cross point with respect to a transition waveform of        the other of the output differential signals, sampling and        measuring the signals based on a multiphase strobe signal of a        known timing, converting the signals into code data, and then        outputting the code data as two bits of timing information;    -   cross point calculation means (e.g., cross point calculation        section 200) for specifying a position of intersection of both        straight lines as cross point information Tcross, the straight        lines being a first straight line which passes between the two        bits of timing information obtained from the transition waveform        of one of the output differential signals, and a second straight        line which passes between the two bits of timing information        obtained from the transition waveform of the other of the output        differential signals;    -   data transition time information collection means (e.g., data        measurement section 300) for receiving the other data signal        DATA output from the DUT, converting the signal into a logical        signal at a predetermined threshold level Vref, sampling and        measuring the signal based on a multiphase strobe signal of a        known timing, converting the signal into code data indicating        timing information of one of rising and falling of the data        signal DATA, and then outputting the code data as data change        point information Tdata;    -   phase difference calculation means (e.g., phase difference        calculation section 400) for obtaining and outputting a relative        phase difference ΔT between the cross point information Tcross        and the data change point information Tdata; and    -   PASS/FAIL determination means (e.g., PASS/FAIL determination        section 500) for receiving the phase difference ΔT, and        executing PASS/FAIL determination to decide whether the phase        difference is within a phase difference standard of the DUT type        or not.

Next, fourth solving means will be described. FIGS. 4 and 1 show solvingmeans concerning the invention.

To solve the problem, a semiconductor test apparatus in which a deviceunder test outputs differential signals (e.g., positive and negativeclock signals) and at least one data signal DATA synchronized therewith,and which comprises a constitution of individually receiving thepositive and negative differential signals in a single end form(unbalanced form) from an analog comparator, and highly accuratelymeasures a relative phase difference between a cross point and the datasignal DATA when a timing of the cross point of the two positive andnegative differential signals output from the DUT is a reference, ischaracterized by comprising:

-   -   first transition information measurement means (e.g., first        transition time information collection means 100#1) for        converting the signals into logical signals at predetermined two        low and high threshold levels for generating a cross point with        respect to a transition waveform of one of the output        differential signals, sampling and measuring the signals based        on a multiphase strobe signal of a known timing, converting the        signals into code data, and then outputting the code data as        first timing information T1 and second timing information T2;    -   second transition information measurement means (e.g., second        transition time information collection means 100#2) for        converting the signals into logical values at predetermined two        high and low threshold levels for generating a cross point with        respect to a transition waveform of the other of the output        differential signals, sampling and measuring the signals based        on a multiphase strobe signal of a known timing, converting the        signals into code data, and then outputting the code data as        third timing information T3 and fourth timing information T4;    -   cross point calculation means (e.g., cross point calculation        section 200) for obtaining a position of intersection of both        straight lines as cross point information Tcross, the straight        lines being a first straight line through which one transition        waveform passes based on the first timing information T1 and the        second timing information T2 obtained therefrom, and a second        straight line through which the other wave form passes based on        the third timing information T3 and the fourth timing        information T4 obtained therefrom;    -   data transition time information collection means (e.g., data        measurement section 300) for receiving the data signal DATA        output from the DUT, converting the signal into a logical signal        at a predetermined threshold level Vref, then sampling and        measuring the signal based on a multiphase strobe signal of a        known timing, converting the signal into code data indicating a        rising or falling timing of the data signal DATA, and outputting        the code data as data change point information Tdata;    -   phase difference calculation means (e.g., phase difference        calculation section 400) for obtaining and outputting a relative        phase difference ΔT between the cross point information Tcross        and the data change point information Tdata; and    -   PASS/FAIL determination means (e.g., PASS/FAIL determination        section 500) for receiving the obtained phase difference ΔT, and        executing PASS/FAIL determination to decide whether the phase        difference is within a phase difference standard (e.g., maximum        phase difference Tmax, minimum phase difference Tmin) for the        DUT type.

Next, fifth solving means will be described. FIGS. 5 a to 5 c showsolving means concerning the invention.

To solve the problems, a semiconductor test apparatus which highlyaccurately measures a timing of a cross point of differential signalsoutput from a device under test is characterized by comprising:

-   -   first transition information measurement means (e.g., first        transition time information collection means 100#1) for        converting the signals into logical signals at predetermined        threshold levels VOH, VOL for measuring two points before and        after the cross point with respect to a transition waveform of        one of the output differential signals, sampling and measuring        the signals based on a multiphase strobe signal of a know        timing, converting the signals into code data, and outputting        the code data as two bits of timing information;    -   second transition information measurement means (e.g., second        transition time information collection means 100#2) for        converting the signals into logical values at predetermined        threshold levels VOH, VOL for measuring two points before and        after the cross point with respect to a transition waveform of        the other of the output differential signals, sampling and        measuring the signals based on a multiphase strobe signal of a        known timing, converting the signals into code data, and then        outputting the code data as two bits of timing information; and    -   cross point calculation means (e.g., cross point calculation        section 200) for specifying a position of intersection of both        straight lines as cross point information Tcross, the straight        lines being a first straight line which passes between the two        bits of timing information obtained from the transition waveform        of one of the output differential signal, and a second straight        line which passes between the two bits of timing information        obtained from the transition waveform of the other of the output        differential signals.

Thus, the cross point of the differential signals can be accuratelyspecified.

Next, sixth solving means will be described. FIG. 1 shows solving meansconcerning the invention.

The semiconductor test apparatus is characterized in that a mode of thetransition information measurement means (e.g., first transition timeinformation collection means 100#1, second transition time informationcollection means 100#2) comprises: a first analog comparator CP1, firstmultiphase strobe means 10 and a first edge detection section 52 forgenerating the fist timing information T1; and a second analogcomparator CP2, second multiphase strobe means 10 and a second edgedetection section 51 for generating the second timing information T2.

The first analog comparator CP1 receives the signal output from the DUT,converts the signal into a logical signal at a predetermined low levelVOL, and supplies the logical signal to the first multiphase strobemeans 10.

The first multiphase strobe means 10 receives the logical signal fromthe first analog comparator CP1, generates multistrobe signals of aplurality of m to which a very small phase difference is given therein,samples the logical signal based on the generated multistrobe signals ofthe plurality of m, and outputs a low-side holding signal LD#i (i=1 tom) of a plurality of m bits.

The first edge detection section 52 is a data encoder which receives thelow-side holding signal LD#i of the plurality of m bits, encodes andconverts an m-bit input into an n-bit output based on an edge selectingsignal S2 for selecting a rising or falling edge direction, and outputsthe n-bit data as the first timing information T1.

The second analog comparator CP2 receives the signal output from theDUT, converts the signal into a logical signal at a predetermined highlevel VOH, and supplies the logical signal to the second multiphasestrobe means 10.

The second multiphase strobe means 10 receives the logical signal fromthe second analog comparator CP2, generates multistrobe signals of aplurality of m to which a very small phase difference is given therein,samples the logical signal based on the generated multistrobe signals ofthe plurality of m, and outputs a high-side holding signal HD#i of aplurality of m bits.

The second edge detection section 51 is a data encoder which receivesthe high-side holding signal HD#i of the plurality of m bits, encodesand converts an m-bit input into an n-bit output based on an edgeselecting signal S2 for selecting a rising or falling edge direction,and outputs the n-bit data as the second timing information T2.

Next, seventh solving means will be described. FIG. 1 shows solvingmeans concerning the invention.

The semiconductor test apparatus is characterized in that a mode of thedata transition time information measurement means (e.g., datameasurement section 300) comprises an analog comparator, multi-phasestrobe means 10, a first edge detection section, a second edge detectionsection, and a multiplexer 350 for generating the timing information T1.

The analog comparator receives the data signal DATA of thenon-differential signals output from the DUT, converts the signal into alogical signal at a predetermined threshold level Vref, and supplies thelogical signal to the multiphase strobe means 10.

The multiphase strobe means 10 receives the logical signal from theanalog comparator, generates multistrobe signals of a plurality of m towhich a very small phase difference is given therein, samples thelogical signal based on the generated multistrobe signals of theplurality of m, and outputs a holding signal D#i (i=1 to m) of aplurality of m bits.

The first edge detection section is a data encoder which receives theholding signal D#i of the plurality of m bits, encodes and converts anm-bit input into an n-bit output based on an edge selecting signal S2for selecting a rising edge direction, and outputs the n-bit data as onetiming information Tdh of the rising side.

The second edge detection section is a data encoder which receives theholding signal D#i of the plurality of m bits, encodes and converts anm-bit input into an n-bit output based on an edge selecting signal S2for selecting a falling edge direction, and outputs the n-bit data asthe other timing information Td1 of the falling side.

The multiplexer 350 receives the one timing information Tdh of therising side and the other timing information Td1 of the falling side,selects one of the bits of timing information based on a data edgeselecting signal S3 for selecting a data edge, and outputs theinformation as data change point information Tdata.

Next, eighth solving means will be described. FIG. 12 shows solvingmeans concerning the invention.

The semiconductor test apparatus is characterized in that a mode of thedata transition time information measurement means (e.g., datameasurement section 300) comprises an analog comparator, multi-phasestrobe means 10, and an edge detection section for generating the timinginformation T1.

The analog comparator receives the data signal DATA of thenon-differential signals output from the DUT, converts the signal into alogical signal at a predetermined threshold level Vref, and supplies thelogical signal to the multiphase strobe means 10.

The multiphase strobe means 10 receives the logical signal from theanalog comparator, generates multistrobe signals of a plurality of m towhich a very small phase difference is given therein, samples thelogical signal based on the generated multistrobe signals of theplurality of m, and outputs a holding signal D#i of a plurality of mbits.

The edge detection section is a data encoder which receives the holdingsignal D#i of the plurality of m bits, encodes and converts an m-bitinput into an n-bit output based on a data edge selecting signal S3 forselecting a rising or falling edge direction, and outputs the n-bit dataas data change point information Tdata.

Next, ninth solving means will be described. FIG. 3 and FIGS. 5 a to 5 cshow solving means concerning the invention.

The semiconductor test apparatus is characterized in that according to amode of the cross point calculation means (e.g., cross point calculationsection 200), the cross point information Tcross is generated to beoutput by calculating Tcross={(T2×T4)−(T1×T3)}/{(T2−T1)+(T4−T3)} inwhich T1 is the first timing information obtained by the firsttransition information measurement means, T2 is the second timinginformation, T3 is the third timing information obtained by the secondtransition information measurement means, and T4 is the fourth timinginformation.

Next, tenth solving means will be described. FIG. 11 shows solving meansconcerning the invention.

The semiconductor test apparatus is characterized in that a mode of thecross point calculation means comprises a cross point conversion memory250 for data conversion, and the cross point conversion memory 250prestores cross point information Tcross corresponding to the arithmeticoperation therein, supplies data of bits of timing information T1, T2,T3 and T4 to an address input terminal, and outputs data read by theaddress input terminal as cross point information Tcross in which T1 isthe first timing information obtained by the first transitioninformation measurement means, T2 is the second timing information, T3is the third timing information obtained by the second transitioninformation measurement means, and T4 is fourth timing information.

Next, eleventh solving means will be described. FIG. 3 shows solvingmeans concerning the invention.

The semiconductor test apparatus is characterized in that according to amode of the phase difference calculation means (e.g., phase differencecalculation section 400), the cross point information Tcross from thecross point calculation means and the data change point informationTdata from the data transition time information collection means (e.g.,data measurement section 300) are received, and a relative phasedifference ΔT obtained by calculating a difference between both data, ora phase difference ΔT obtained as a result of adding a predeterminedoffset amount (offset time Toffset) to the phase difference ΔT isoutput.

Next, twelfth solving means will be described. FIG. 3 shows solvingmeans concerning the invention.

The semiconductor test apparatus is characterized in that according to amode of the PASS/FAIL determination means (e.g., PASS/FAIL determinationsection 500), the relative phase difference ΔT is received from thephase difference calculation means, and DUT PASS/FAIL determination ismade to decide whether the phase difference is within a permissiblerange from a predetermined maximum phase difference Tmax to apredetermined minimum phase difference Tmin for executing the DUTPASS/FAIL determination.

Next, thirteenth solving means will be described. FIG. 10 shows solvingmeans concerning the invention.

The semiconductor device is characterized by further comprisingPASS/FAIL determination control means in addition to the cross pointcalculation means and the PASS/FAIL determination means, and in that:

-   -   the PASS/FAIL determination control means causes the cross point        calculation means to generate a data error signal Derr by        understanding that a normal cross point has not been measured        when a data value of at least one of the four bits of timing        information, i.e., the first timing information T1, the second        timing information T2, the third timing information T3, and the        fourth timing information T4, output from the transition        information measurement means (e.g., first transition time        information collection means 100#1, second transition time        information collection means 100#2) is “0”, and the PASS/FAIL        determination means comprises means for controlling the inside        not to execute PASS/FAIL determination when the data error        signal Derr is received.

Next, fourteenth solving means will be described. FIG. 9 shows solvingmeans concerning the invention.

To solve the problems, a semiconductor test apparatus which highlyaccurately measures a relative phase difference between a cross pointand the other data signal DATA output from a device under test (DUT) byusing a timing of the cross point of differential signals output fromthe DUT as a reference is characterized by comprising:

-   -   first transition information measurement means (e.g., first        transition time information collection means 100#1) for        converting the signals into logical signals at predetermined two        low and high threshold levels, sampling and measuring the        signals based on a multiphase strobe signal of a known timing,        converting the signals into code data, and then outputting the        code data as first timing information T1 and second timing        information T2;    -   second transition information measurement means (e.g., second        transition time information collection means 100#2) for        converting the signals into logical values at predetermined two        high and low threshold levels with respect to a transition        waveform of the other of the output differential signals,        sampling and measuring the signals based on a multiphase strobe        signal of a known timing, converting the signals into code data,        and then outputting the code data as third timing information T3        and fourth timing information T4;    -   data transition time information collection means (e.g., data        measurement section 300) for receiving the data signal DATA        output from the DUT, converting the signal into a logical signal        at a predetermined threshold level Vref, sampling and measuring        the signal based on a multiphase strobe signal of a known        timing, converting the signal into code data indicating a rising        or falling timing of the data signal DATA, and then outputting        the code data as data change point information Tdata;    -   edge data storage means (e.g., edge data storage memory 700) of        a predetermined storage capacity for measuring, by a        predetermined number of times, and storing the two bits of        timing information measured by the first transition information        measurement means, the two bits of timing information measured        by the second transition information measurement means, and one        bit of timing information measured by the data transition time        information collection means; and    -   cross point calculation/PASS/FAIL determination processing means        (e.g., cross point calculation/phase difference        calculation/PASS/FAIL determination processing section 650) for        reading data contents of the edge data storage means,        calculating a relative phase difference ΔT between cross point        information Tcross obtained by calculating the cross point by        software and the data change point information Tdata, executing        the arithmetic operation by the number of times corresponding to        the number of measuring times, and making PASS/FAIL        determination to decide whether a plurality of obtained phase        differences ΔT are within a phase difference standard of the DUT        type or not.

Next, fifteenth solving means will be described. FIG. 9 shows solvingmeans concerning the invention.

The semiconductor test apparatus is characterized by further comprisinga function of receiving the plurality of phase differences ΔT obtainedby the cross point calculation/PASS/FAIL determination processing meanscorresponding to the number of measuring times, and obtaining afluctuation amount of the plurality of phase differences ΔT to specify ajitter amount between both signals.

Thus, according to the invention, the components of the solving meansmay be properly combined to constitute other practical constitutionswhen desired. Moreover, reference numerals given to the componentscorrespond to those of the embodiment of the invention, but thereference numerals are not limited to such. Other practical equivalentsmay be employed as components.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a view showing a main portion block constitutional example ofa semiconductor test apparatus when a differential clock signal and asingle end data signal DATA output from a DUT are received, and arelative phase difference therebetween is obtained to determinePASS/FAIL;

FIGS. 2 a and 2 b are views showing an encoding example of an edgedetection section and a circuitry example in the case of m=4;

FIG. 3 is a view showing a specific internal constitutional example of across point calculation section 200;

FIG. 4 is a simple timing chart showing bits of timing information T1 toT4, Tdh when strobe signals STRB1 to STRB4 are generated by the samereference timing T0;

FIGS. 5 a to 5 c are views explaining calculation of cross pointinformation;

FIGS. 6 a and 6 b are views showing a principle circuit connection whenhigh-speed data transfer is executed between two devices on a circuitboard in synchronization with a differential clock, and a main portionof the semiconductor test apparatus which comprises a single endcomparator CP to receive each of a positive clock signal CLKP and anegative clock signal CLKN which are differential clock signals outputfrom the DUT;

FIGS. 7 a to 7 d are views explaining a cross point in the case of anideal differential signal, a cross point in an actual differentialsignal example, and inphase and reversed phase changes between bothsignals, i.e., a differential clock signal CLK and a data signal DATA,caused by jitters or the like;

FIG. 8 is a timing chart showing an example in the case of a narrowpulse width;

FIG. 9 is a view showing another main portion block constitutionalexample of the semiconductor test apparatus when a differential clocksignal and a single end data signal DATA output from the DUT arereceived, and a relative phase difference therebetween is obtained todetermined PASS/FAIL;

FIG. 10 is a view showing yet another main portion block constitutionalexample of the semiconductor test apparatus when a differential clocksignal and a single end data signal DATA output from the DUT arereceived, and a relative phase difference therebetween is obtained todetermine PASS/FAIL;

FIG. 11 is a view showing yet another main portion block constitutionalexample when a differential clock signal and a single end data signalDATA output from the DUT are received, and a relative phase differencetherebetween is obtained to determine PASS/FAIL;

FIG. 12 is a view showing another constitutional example of a datameasurement section 300; and

FIG. 13 is a view showing another constitutional example in which arelative phase difference between two types of differential signals isobtained to determine PASS/FAIL.

BEST MODE FOR CARRYING OUT THE INVENTION

Next, an embodiment of the present invention will be described withreference to the accompanying drawings. The describe contents of theembodiment are not limitative of appended claims. Elements, connectionrelations or the like are not essential to solving means. Further,adjective patterns/forms of the elements, the connection relations orthe like of the embodiment are only examples but not limitative of theinvention.

The invention will be described with reference to FIGS. 1 to 13.

FIG. 1 shows a main portion block constitutional example of asemiconductor test apparatus when a differential clock signal and asingle end data signal DATA output from a DUT are received, and arelative phase difference therebetween is obtained to determinePASS/FAIL. Incidentally, an entire constitution of the semiconductortest apparatus is described in Japanese Patent Application No.2000-178917, and thus explanation thereof will be omitted.

As components, the semiconductor test apparatus comprises firsttransition time information collection means 100#1, second transitiontime information collection means 100#2, third transition timeinformation collection means 100#3, a multiplexer 350, a cross pointcalculation section 200, a phase difference calculation section 400, andPASS/FAIL determination section 500. A data measurement section 300comprises the third transition time information collection means 100#3and the multiplexer 350.

The first transition time information collection means 100#1 receivesone positive clock signal CLKP of differential clock signals output froma DUT, converts the signal into a logical signal at two threshold levelsVOH, VOL of a high side and a low side, then measures bits of timinginformation before and after transition of the logical signal bymultiphase STB based on strobe signals STRB2, STRB1, and generates andoutputs bits of timing information T2, T1 converted into code data whichbecome time information. This internal element comprises high-sidemultiphase strobe means 21, low-side multiphase strobe means 22, andedge detection sections 51, 52.

The high-side multiphase strobe means 21 outputs m-bit high-side holdingsignals HD#1 to HD#m obtained as a result of sampling logical signalsconverted at the high-side threshold level VOH by individual timings ofm points by the multiphase STB (multiphase strobe signal) based on thestrobe signal STRB2. An internal constitutional example comprises acomparator CP2 and multiphase strobe means 10. This constitution will bedescribed with reference to a timing chart of FIG. 4. FIG. 4 is a simpletiming chart showing bits of timing information T1 to T4, Tdh whenstrobe signals STRB1 to STRB4 are generated by the same reference timingT0.

The multiphase strobe means 10 receives one strobe signal STRB2 from atiming generator TG (not shown), finely delays the signal in atime-sequential manner to generate multiphase STB (see FIG. 4) of mpoints, samples logical signals CP2 s output from the comparator CP2 bym pieces of timing comparators TC based on the generated STB of mpoints, and outputs m-bit high-side holding signals HD#1 to HD#m as aresult of the sampling. Here, for a value of m, 16 points/32 points orthe like are used. If a 20 pico-second pitch is applied, a fine delayamount can be obtained as fine pitch time information continuous over asection of 32 points×20 pico-seconds=640 pico-seconds. On the otherhand, for the strobe signal STRB2 and each multiphase STB, a knowntiming can be set by calibration. Further, the strobe signal STRB2 canbe generated and controlled by movement to an optional timing. Thus, asshown in FIG. 4, even the multiphase STB of a limited section can besampled by moving the strobe signal STRB2 to positions before and afterthe high-side threshold level VOH of the positive clock signal CLKP.

An edge detection section 51 is a data encoder which comprises afunction of selecting a rising or falling edge, and converts an m-bitinput into an n-bit output. This will be described with reference to anencoding example of the edge detection section in the case of m=4 bitsof FIG. 2 a, and a circuitry example of FIG. 2 b.

In FIG. 2 a, first, encoding is executed by targeting a rising edge whenan edge selecting signal S2 is “0”. When input data is time-sequentialdata of “0111” (see A in FIG. 2 a), the data is converted into anencoded 2-bit code data “1” and output. Similarly, when input data istime-sequential data of “0011” (see B in FIG. 2 a), code data “2” isoutput. Similarly, when input data is time-sequential data of “0001”(see C in FIG. 2 a), code data “3” is output.

Second, encoding is executed by targeting a falling edge when an edgeselecting signal S2 is “1”. As in the case of the foregoing, when inputdata is time-sequential data of “1000” (see A in FIG. 2 a), code data“1” is output. Similarly, when input data is time-sequential data of“1100” (see B in FIG. 2 a), code data “2” is output. Similarly, wheninput data is time-sequential data of “1110” (see C in FIG. 2 a), codedata “3” is output.

The circuitry example of FIG. 2 b is an example to realize theaforementioned operation. A rising change or a falling change of thetime-sequential data is detected and output by 6 AND gates of aninversion input terminal of one side, one of the rising change and thefalling change is selected and output by 3 multiplexers and the edgeselecting signal S2, and the 3-bits detected data is converted into2-bit code data by a priority encoder and output as timing informationT2.

Now, a case of a narrow pulse width shown in FIG. 8 will be described.In the multiphase STB section, both of rising and falling sides of thepositive clock signal CLKP may be present. However, by the edgeselecting signal S2, a rising edge A or a falling edge B in FIG. 8 canbe specified as a target of conversion. Accordingly, target code datacan be generated without any troubles under such conditions.

Next, the low-side multiphase strobe means 22 shown in FIG. 1 is similarto the high-side multiphase strobe means 21, and outputs m-bit low-sideholding signals LD#1 to LD#m obtained as a result of sampling logicalsignals converted at the low-side threshold level VOL by individualtimings of m points by the multiphase STB based on the strobe signalSTRB1. Incidentally, the strobe signal STRB1 and the strobe signal STRB2may be shared by one strobe signal.

An edge detection section 52 is similar to the edge detection section51, comprises a function of selecting a rising or falling edge, convertsan m-bit input into an n-bit code data, and outputs the code data astiming information T1.

The second transition time information collection means 100#2 is similarto the first transition time information collection means 100#1,receives the other negative clock signals CLKN of the differential clocksignals output from the DUT, converts the signals into logical signalsat the high and low-side 2 threshold levels VOH, VOL, measures thesignals by multiphase STB based on strobe signals STRB3, STRB4, andgenerates and outputs bits of timing information T3, T4 converted intocode data which become time information.

The third transmission time information collection means 100#3 is almostsimilar to the first transition time information collection means 100#1,receives the data signal DATA output from the DUT, converts the signalinto a logical signal at an intermediate threshold level Vref as shownin the lower side of the timing chart of FIG. 4, then measures thesignal by multiphase STB based on strobe signals STRB5, STRB6, andgenerates and outputs bits of timing information Tdh, Td1 converted intocode data which become time information. At this time, there may be anoffset time Toffset between the strobe signals STRB5, STRB6 and thestrobe signals STRB1 to STRB4 with respect to the reference timing T0shown in FIG. 4. However, the offset time Toffset is known timeinformation since the strobe signals STRB1 to STRB6 are known timings.

Since the third transition time information collection means 100#3 onlyneeds convert the signals into the logical signals at the same thresholdlevels Vref, this internal component may comprise one multiphase strobemeans 10 only shown in FIG. 1, share the output signal thereof, andsupply the signal to both of the edge detection sections 51 and 52.

The data measurement section 300 that comprises the third transitiontime information collection means 100#3 and the multiplexer 350 onlyneeds sample the signals converted into the logical signals at the samethreshold level Vref by one type of multiphase STB. The measurementsection can accordingly be constituted as shown in the otherconstitutional example of a data measurement section of FIG. 12. Inother words, the constitution can be realized by the high-sidemultiphase strobe means 21 and the edge detection section 51. That is,by one high-side multiphase strobe means 21, signals are converted intological signals at a threshold level Vref, holding signals D#1 to D#moutput therefrom are supplied to the edge detection section 51, and datachange point information Tdata of a rising side edge or a falling sideedge selected based on a data edge selecting signal S3 is output. Thisconstitutional example can be more inexpensive.

The multiplexer 350 shown in FIG. 1 is a data selector of a 2-input1-output type and an n-bit width, and supplies the data change pointinformation Tdata obtained as a result of selecting the rising edgetiming information Tdh or the falling edge timing information Td1generated by the third transition time information collection means100#3 to the phase difference calculation section 400 based on the dataedge selecting signal S3.

The cross point calculation section 200 calculates a cross point basedon the two bits of timing information T1, T2 of the positive clocksignal CLKP side and the two bits of timing information T3, T4 of thenegative clock signal CLKN side. This will be described with referenceto calculation explanatory views of cross point information Tcross ofFIGS. 5 a to 5 c. The calculation is executed by assuming that waveformschange almost linearly in a waveform section of the timing informationT1 and T2 and a waveform section of the timing information T3 and T4.

The cross point information Tcross of FIG. 5 a can be obtained by acomputing equation of Tcross={(T2×T4)−(T1×T3)}/{(T2−T1)+(T4-T3)}.

Incidentally, even in the case of irregular bits of timing informationT1 to T4 of FIG. 5 c, the cross point information can be obtained by thecomputing equation. This means that a desired linear waveform portioncan be measured in a waveform section of clock transition.

FIG. 3 shows a specific internal constitutional example of the crosspoint calculation section 200. The constitutional example comprises twomultipliers, three subtracters, one adder, and one divider correspondingto the computing equation. Based on data obtained as a result of thecalculation, desired n-bit cross point information Tcross is supplied tothe phase difference calculation section 400. Incidentally, since thecalculation time is about several hundred nano-seconds, the samplingmeasurement of the DUT is executed at a cycle of a corresponding time ormore. Depending on DUT characteristics, DUT evaluation can bepractically carried out by practically repeating, e.g., samplingmeasurement of several thousand times or more and PASS/FAILdetermination.

The phase difference calculation section 400 shown in FIG. 1 obtains arelative phase difference ΔT between both signals, i.e., the cross pointof the differential clock signal CLK and the data signal DATA. That is,the phase difference calculation section 400 receives the cross pointinformation Tcross and the data change point information Tdata obtainedas described above, calculates a phase difference ΔT therebetween, andsupplies it to the PASS/FAIL determination section 500. In actualmeasurement of the semiconductor test apparatus, strobe signals ofindividual timings are used. Thus, an offset time Toffset which is atime difference between the strobe signals is applied to calculate aphase difference ΔT. Accordingly, for the phase difference ΔT, anarithmetic operation of ΔT=(Tdata+Toffset)−Tcross is executed.Incidentally, since the offset time Toffset varies depending on a DUTtype standard, a positive, negative or zero value can be taken.

The PASS/FAIL determination section 500 determines PASS within a phasedifference standard of the DUT type, and FAIL outside the range. Thatis, based on a maximum phase difference Tmax and a minimum phasedifference Tmin of the DUT standard, the phase difference ΔT obtainedabove is compared. PASS is determined in the case of Tmim≦ΔT≦Tmax, andFAIL is determined in other cases.

According to the invention constitutional example of FIG. 1, theconstitution comprises the means for determining PASS/FAIL by specifyingthe cross point of the differential cross signals CLK at the samemeasuring time, obtaining the phase difference between both signals,i.e., the cross point and the data signal DATA, and determining whetherthe obtained phase difference is within the predetermined standard ornot. Thus, a great advantage can be provided which can accuratelydetermine PASS/FAIL of the relative phase difference between the twosignals based on the cross point of the differential clock signals.Needless to say, even when there are instantaneous jitters orfluctuation between the two signals, the PASS/FAIL can be accuratelydetermined.

A technical idea of the invention is not limited to the specificconstitutional example, the connection form example of theaforementioned embodiment. Further, based on the technical ideal of theinvention, the embodiment can be properly modified to be widely used.

The constitutional example of FIG. 1 has been described by taking thespecific example of the differential clock signal CLK. However, theconstitutional example can be applied to differential signals other thanthe clock signal CLK.

The constitutional example of FIG. 1 has been described by taking thespecific example of testing the phase difference under the signalconditions of the 1-channel differential clock signal CLK and the1-channel data signal DATA. However, the constitutional example may beapplied to the other signal conditions. The first example is anotherconstitutional example shown in FIG. 13 in which the relative phasedifference between the two types of differential signals is obtained todetermine the PASS/FAIL. To enable testing of the phase differencebetween the two types of differential signals, by disposing two types ofcross point measurement sections 600 shown in FIG. 1, it is possible todetermine PASS/FAIL of a phase difference between the types ofdifferential signals. The second example is that the plurality of datameasurement sections 300 shown in FIG. 1 to measure the data signal DATAare disposed, the phase difference calculation section 400 and thePASS/FAIL determination section 500 are disposed corresponding to themeasurement sections, and thus relative phase differences of a pluralityof types of data signals DATA can be subjected to PASS/FAILdetermination altogether.

Depending on the DUT device type, the differential signal such as adifferential clock signal which is a testing target is normally aspecific signal of one channel or about several channels. Accordingly,for the number of channels of the aforementioned constitution disposedin the semiconductor test apparatus, the number of channelscorresponding to the DUT is enough.

In the case of simultaneously testing a differential clock signal of onechannel and data signals DATA of a plurality of channels, it is onlynecessary to employ a corresponding constitution which comprises a datameasurement section 300 of a plurality of channels, a phase differencecalculation section 400 and PASS/FAIL determination section 500corresponding to the data measurement section 300 of the plurality ofchannels.

The constitutional example of FIG. 1 is a specific example in which allare realized by the circuits. However, the invention is not limited tosuch. For example, the apparatus can be realized by anotherconstitutional example shown in FIG. 9. According to this constitutionalexample, the cross point calculation section 200, the phase differencecalculation section 400 and the PASS/FAIL determination section 500 ofFIG. 1 are removed and, instead, an edge data storage memory 700, anaddress generations section 620, and a cross point calculation/phasedifference calculation/PASS/FAIL determination processing section 650are added.

The edge data storage memory 700 is a memory of a desired capacity, andstores bits of timing information T1 to T4 and data change pointinformation Tdata altogether for each sampling measurement. Accordingly,sampling measurement results of many times can be stored.

The address generation section 620 generates addresses for the memory,and generates an address signal whose address value is incremented by 1by an INC signal for each sampling measurement, and supplies the signalto the edge data storage memory 700.

The cross point calculation/phase difference calculation/PASS/FAILdetermination processing section 650 calculates a cross point bysoftware to make determination, sequentially reads edge data stored inthe edge data storage memory 700, calculates cross point informationTcross by software, calculates a phase difference ΔT by software,determines PASS/FAIL of the phase difference ΔT based on a maximum phasedifference Tmax and a minimum phase difference Tmin of an expectedvalue, and outputs a determination result of PASS/FAIL as in the case ofthe constitutional example of FIG. 1.

Therefore, an advantage of reducing the circuit size more than theconstitutional example of FIG. 1 can be obtained.

Additionally, the cross point calculation section 200 shown in FIG. 3may comprise pipeline circuitry or an interleave constitution tocalculate in synchronization with a clock when desired. In this case, itis possible to greatly reduce the sampling cycle of repeated samplingmeasurement.

FIG. 11 shows another constitutional example. According to thisconstitutional example, a cross point conversion memory 250 for dataconversion is disposed in place of the cross point calculation section200 of the constitution of FIG. 1. The cross point conversion memory 250supplies input data of bits of timing information T1 to T4, therebyreads contents of a specified address, and outputs the contents as crosspoint information Tcross. In the case of n=5 bits, a memory (RAM/ROM) ofan address space of 5×4=20 bits is disposed. Here, contents of thememory are prestored so that the cross point information Tcross can beread. Accordingly, a function similar to that of the cross pointcalculation section 200 can be realized.

FIG. 10 shows another constitutional example. According to this example,the cross point calculation section 200 and the PASS/FAIL determinationsection 500 of the constitution of FIG. 1 are changed to a cross pointcalculation section 201 and PASS/FAIL determination section 501. Sinceno cross point is detected when one of input bits of timing informationT1 to T4 is “0”, the cross point calculation section 201 generates adata error signal Derr understanding that sampling measurement has notbeen executed in a normal position. The PASS/FAIL determination section501 controls the inside so as not to execute PASS/FAIL determinationwhen it receives the data error signal Derr.

Accordingly, as a result of PASS/FAIL determination executed only whenthe sampling measurement is carried out in the normal position, forexample, when the differential clock signal CLK and a test cycle (testrate) of the semiconductor test apparatus are in an asynchronousrelation to each other, or when large fluctuation occurs in the clockfrequency of the differential clock signal CLK, sampling measurement canbe normally executed at a fixed probability frequency. Thus, a greatadvantage can be provided which enables accurate PASS/FAIL determinationwhen the sampling measurement can be normally executed.

Furthermore, for the portions practically applied to the aforementionedcomponents or the functional means for realization, constituting meansmay be employed to realize the portions based on both of software or amicroprogram and a hardware logic, or constituting means for realizationbased on software may be employed.

INDUSTRIAL APPLICABILITY

As apparent from the foregoing, the present invention has the followingeffects.

As described above, according to the invention, the constitution isemployed which comprises the means for determining PASS/FAIL byspecifying the cross point of the differential clock signals CLK at thesame measurement time, obtaining the phase difference between bothsignals, i.e., the cross point and the data signal DATA, and determiningwhether the obtained phase difference is within a predetermined standardor not. Thus, the invention can provide a great advantage that it ispossible to accurately determine PASS/FAIL of a relative phasedifference between both signals based on the cross point of thedifferential clock signals.

Additionally, according to the constitutional example of FIG. 10, theinvention can provide an advantage that as a result of execute PASS/FAILdetermination only when sampling measurement is carried out in a normalposition, even in the case of an asynchronous relation between thedifferential clock signal CLK and the test cycle (test rate) of thesemiconductor test apparatus, it is possible to accurately determinePASS/FAIL based on a result of proper sampling measurement.

Thus, technical effects of the invention are great, and industrialeconomic effects are also large.

1. A semiconductor test apparatus characterized by comprising:differential signal timing measurement means for outputting cross pointinformation Tcross obtained by measuring a timing of a cross point ofone of differential signals output from a device under test (DUT);non-differential signal timing measurement means for outputting datachange point information Tdata obtained by measuring a timing oftransition of a logic of the other non-differential signal output fromthe DUT; phase difference calculation means for outputting a phasedifference ΔT obtained by calculating a relative phase differencebetween the cross point information Tcross and the data change pointinformation Tdata which are obtained by simultaneously measuring both ofthe output signals; and PASS/FAIL determination means for determiningPASS/FAIL of a relative positional relation of the DUT based onpredetermined upper and lower limit threshold values for executingpass/fail determination upon reception of the phase difference ΔT or oneof the threshold values.
 2. A semiconductor test apparatus characterizedby comprising: first differential signal timing measurement means foroutputting first cross point information Tcross obtained by measuring atiming of a cross point of first differential signals output from adevice under test (DUT); second differential signal timing measurementmeans for outputting second cross point information Tcross obtained bymeasuring a timing of a cross point of second differential signalsoutput from the DUT; phase difference calculation means for outputting aphase difference ΔT obtained by calculating a relative phase differencebetween the first cross point information Tcross and the second crosspoint information Tcross which are obtained by simultaneously measuringboth of the output differential signals; and PASS/FAIL determinationmeans for determining PASS/FAIL of the DUT upon reception of the phasedifference ΔT based on predetermined upper and lower limit thresholdvalues corresponding to the DUT whose PASS/FAIL is determined or one ofthe threshold values.
 3. The semiconductor test apparatus according toclaim 1, characterized in that: the differential signal timingmeasurement means comprises first transition information measurementmeans for converting the signals into logical signals at predeterminedthreshold levels for measuring two points before and after the crosspoint with respect to a transition waveform of one of the outputdifferential signals, sampling and measuring the signals based on amultiphase strobe signal, then converting the signals into code data,and outputting the code data as two bits of timing information, secondtransition information measurement means for converting the signals intological values at predetermined threshold levels for measuring twopoints before and after the cross point with respect to a transitionwaveform of the other of the output differential signals, sampling andmeasuring the signals based on a multiphase strobe signal, thenconverting the signals into code data, and outputting the code data astwo bits of timing information, and cross point calculation means forspecifying a position of intersection of both straight lines as crosspoint information Tcross, the straight lines being a first straight linewhich passes between the two bits of timing information obtained fromthe transition waveform of one of the output differential signals, and asecond straight line which passes between the two bits of timinginformation obtained from the transition waveform of the other of theoutput differential signals, and the non-differential signal timingmeasurement means comprises data transition time information collectionmeans for receiving the other data signal DATA output from the DUT,converting the signal into a logical signal at a predetermined thresholdlevel, sampling and measuring the signal based on a multiphase strobesignal, converting the signal into code data indicating timinginformation of one of rising and falling of the data signal DATA, andthen outputting the code data as data change point information Tdata. 4.The semiconductor test apparatus according to claim 3, characterized inthat: the first transition information measurement means converts thesignals into logical signals at predetermined two low and high thresholdlevels, samples and measures the signals based on the multiphase strobesignal, converts the signals into code data, and outputs the code dataas first timing signal and second timing signal, the second transitioninformation measurement means converts the signals into logical signalsat predetermined two high and low threshold levels, samples and measuresthe signals based on the multiphase strobe signal, converts the signalsinto code data, and outputs the code data as third timing informationand fourth timing information, and the cross point calculation meansobtains the position of intersection of both straight lines as the crosspoint information Tcross, the straight lines being the first straightline through which one transition waveform passes based on the firsttiming information and the second timing information obtained therefrom,and the second straight line through which the other transition waveformpasses based on the third timing information and the fourth timinginformation obtained therefrom.
 5. A semiconductor test apparatus whichmeasures a timing of a cross point of differential signals output from adevice under test (DUT), characterized by comprising: first transitioninformation measurement means for converting signals into logicalsignals at predetermined threshold levels for measuring two pointsbefore and after the cross point with respect to a transition waveformof one of the output differential signals, sampling and measuring thesignals based on a multiphase strobe signal, converting the signals intocode data, and then outputting the code data as two bits of timinginformation; second transition information measurement means forconverting the signals into logical values at predetermined thresholdlevels for measuring two points before and after the cross point withrespect to a transition waveform of the other of the output differentialsignals, sampling and measuring the signals based on a multiphase strobesignal, converting the signals into code data, and then outputting thecode data as two bits of timing information; and cross point calculationmeans for specifying a position of intersection of both straight linesas cross point information Tcross, the straight lines being a firststraight line which passes between the two bits of timing informationobtained from the transition waveform of one of the output differentialsignals, and a second straight line which passes between the two bits oftiming information obtained from the transition waveform of the other ofthe output differential signals.
 6. The semiconductor test apparatusaccording to claim 4, characterized in that: the cross point calculationmeans comprises a cross point conversion memory for data conversion, andthe cross point conversion memory prestores the cross point informationTcross corresponding to an arithmetic operation therein, supplies dataof the bits of timing information T1, T2, T3 and T4 to an address inputterminal, and outputs data read by the address input terminal as thecross point information Tcross.
 7. The semiconductor test apparatusaccording to claim 3, characterized in that: the phase differencecalculation means receives the cross point information Tcross from thecross point calculation means and the data change point informationTdata from the data transition time information collection means, andoutputs a relative phase difference ΔT obtained by calculating adifference between both data, or a phase difference ΔT obtained as aresult of calculating a predetermined offset amount of the phasedifference ΔT.
 8. The semiconductor test apparatus according to claim 4,further comprising PASS/FAIL determination control means, characterizedin that: the PASS/FAIL determination control means causes the crosspoint calculation means to generate a data error signal Derr when a datavalue of at least one of the four bits of timing information, i.e., thefirst timing information, the second timing information, the thirdtiming information, and the fourth timing information, output from thetransition information measurement means is “0”, and the PASS/FAILdetermination means comprises means for controlling the inside not toexecute PASS/FAIL determination when the data error signal Derr isreceived.
 9. A semiconductor test apparatus which measures a relativephase difference between a cross point and the other data signal DATAoutput from a device under test (DUT) by using a timing of the crosspoint of differential signals output from the DUT as a reference,comprising: first transition information measurement means forconverting the signals into logical signals at predetermined two low andhigh threshold levels, sampling and measuring the signals based on amultiphase strobe signal, converting the signals into code data, andthen outputting the code data as first timing information and secondtiming information; second transition information measurement means forconverting the signals into logical values at predetermined two high andlow threshold levels with respect to a transition waveform of the otherof the output differential signals, sampling and measuring the signalsbased on a multiphase strobe signal, converting the signals into codedata, and then outputting the code data as third timing information andfourth timing information; data transition time information collectionmeans for receiving the data signal DATA output from the DUT, convertingthe signal into a logical signal at a predetermined threshold level,then sampling and measuring the signal based on a multiphase strobesignal, converting the signal into code data indicating a rising orfalling timing of the data signal DATA, and outputting the code data asdata change point information Tdata; and edge data storage means formeasuring, by a predetermined number of times, and storing the two bitsof timing information measured by the first transition informationmeasurement means, the two bits of timing information measured by thesecond transition information measurement means, and one bit of timinginformation measured by the data transition time information collectionmeans, characterized in that data contents of the edge data storagemeans are read, a relative phase difference ΔT between cross pointinformation Tcross obtained by calculating the cross point and the datachange point information Tdata is obtained by calculation, thearithmetic operation is executed by the number of times corresponding tothe number of measuring times, and PASS/FAIL determination is made todecide whether a plurality of obtained phase differences ΔT are within aphase difference standard of the DUT type or not.
 10. The semiconductortest apparatus according to claim 9, further comprising a function ofreceiving the plurality of phase differences ΔT obtained by the crosspoint calculation/PASS/FAIL determination processing means correspondingto the number of measuring times, and obtaining a fluctuation amount ofthe plurality of phase differences ΔT to specify a jitter amount betweenboth signals.